Electronic devices are often tested by generating a plurality of input patterns for the pins of a device under test, applying the input patterns to the device under test, capturing output patterns from the device under test, and then comparing the captured output patterns (or device vectors corresponding thereto) to expected output patterns or vectors.
Each of the afore-mentioned patterns comprises a plurality of sequential states. These states may take a variety of forms, such as logic one (1), logic zero (0), high (H), low (L), or don't care (X).
For some circuit testers, input patterns and expected output patterns are stored in pattern memory as sequences of smaller patterns (e.g., smaller patterns comprising three sequential states of the original pattern); and waveforms corresponding to these smaller patterns are stored in high-speed waveform memories. The patterns stored in the pattern memories are then used to address the waveforms stored in the waveform memories.
Due to the high-speed nature of the waveform memories, these memories are often too small to hold waveforms corresponding to all “potential” patterns stored in pattern memory. Decisions therefore need to be made regarding which waveforms to store in each waveform memory. The United States patent application of Hildebrant entitled “Systems and Methods for Testing Performance of an Electronic Device” (Ser. No. 10/461,252 filed Jun. 12, 2003, hereby incorporated by reference) discloses systems and methods for 1) examining the “actual” patterns that are to be stored in a pattern memory to discern which unique combinations of states are actually found therein, and then 2) using this information as a basis for determining which waveforms should be stored in a corresponding waveform memory.
Sometimes, the frequency at which test data needs to be provided to a device under test (DUT) will exceed the operating frequency of a circuit tester's waveform memories. Some circuit testers therefore have a switching network to associate plural multiplexed waveform memories with a pin of a DUT. Thus, for example, the state-by-state outputs of two waveform memories may be interleaved to provide test data to (or to compare data to an output of) a pin of a DUT, thereby providing the pin or a comparator with test data at twice the rate that one of the waveform memories could provide the test data.